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W9425G6JH
10.6 AC Characteristics and Operating Condition
SYM.
PARAMETER
MIN.
-4
MAX.
-5/-5I/-5A
MIN. MAX.
UNIT
NOTES
t RC
t RFC
Active to Ref/Active Command Period
Ref to Ref/Active Command Period
52
60
55
70
t RAS
Active to Precharge Command Period
36
70000
40
100000
nS
t RCD
t RAP
Active to Read/Write Command Delay Time
Active to Read with Auto-precharge Enable
16
16
15
15
t CCD
t RP
t RRD
t WR
Read/Write(a) to Read/Write(b) Command Period
Precharge to Active Command Period
Active(a) to Active(b) Command Period
Write Recovery Time
1
16
8
15
1
15
10
15
t CK
nS
(t WR /t CK )
(t WR /t CK )
t DAL
Auto-precharge Write Recovery + Precharge Time
+
+
t CK
18
(t RP /t CK )
(t RP /t CK )
CL = 2
-
-
7.5
12
t CK
CLK Cycle Time
CL = 2.5
CL = 3
CL = 4
-
4
4
-
10
10
6
5
-
12
12
-
nS
t AC
t DQSCK
Data Access Time from CLK, CLK
DQS Output Access Time from CLK, CLK
-0.7
-0.6
0.7
0.6
-0.7
-0.6
0.7
0.6
16
16
t DQSQ
Data Strobe Edge to Output Data Edge Skew
0.4
0.4
t CH
t CL
CLk High Level Width
CLK Low Level Width
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
t CK
11
t HP
t QH
CLK Half Period (minimum of actual t CH, t CL )
DQ Output Data Hold Time from DQS
min
(t CL ,t CH )
t HP -0.5
Min,
(t CL ,t CH )
t HP -0.5
nS
t RPRE
t RPST
DQS Read Preamble Time
DQS Read Postamble Time
0.9
0.4
1.1
0.6
0.9
0.4
1.1
0.6
t CK
11
t DS
DQ and DM Setup Time to DQS, slew rate 0.5V/nS
0.4
0.4
t DH
t DIPW
t DQSH
DQ and DM Hold Time to DQS, slew rate 0.5V/nS
DQ and DM Input Pulse Width (for each input)
DQS Input High Pulse Width
0.4
1.75
0.35
0.4
1.75
0.35
nS
t DQSL
t DSS
t DSH
t WPRES
t WPRE
DQS Input Low Pulse Width
DQS Falling Edge to CLK Setup Time
DQS Falling Edge Hold Time from CLK
Clock to DQS Write Preamble Set-up Time
DQS Write Preamble Time
0.35
0.2
0.2
0
0.25
0.35
0.2
0.2
0
0.25
t CK
nS
11
t WPST
t DQSS
DQS Write Postamble Time
Write Command to First DQS Latching Transition
0.4
0.85
0.6
1.15
0.4
0.72
0.6
1.25
t CK
11
t IS
t IH
t IS
t IH
t IPW
t HZ
Input Setup Time (fast slew rate)
Input Hold Time (fast slew rate)
Input Setup Time (slow slew rate)
Input Hold Time (slow slew rate)
Control & Address Input Pulse Width (for each input)
Data-out High-impedance Time from CLK, CLK
0.6
0.6
0.7
0.7
2.2
0.7
0.6
0.6
0.7
0.7
2.2
0.7
nS
19, 21-23
19, 21-23
20-23
20-23
t LZ
t T(SS)
t WTR
t XSNR
t XSRD
Data-out Low-impedance Time from CLK, CLK
SSTL Input Transition
Internal Write to Read Command Delay
Exit Self Refresh to non-Read Command
Exit Self Refresh to Read Command
-0.7
0.5
2
72
200
0.7
1.5
-0.7
0.5
2
75
200
0.7
1.5
t CK
nS
t CK
t REFI
t MRD
Refresh Interval Time (8K/ 64mS)
Mode Register Set Cycle Time
8
7.8
10
7.8
μS
nS
17
Publication Release Date: Aug. 27, 2013
- 26 -
Revision A03
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